Integrated circuits contain a plurality of signal paths which essentially carry information (data and control signals) across the circuit. Each signal path is made up of a plurality of circuit elements connected together serially (i.e., in series). Each of these signal paths experiences a delay as signals travel across the circuit. These signal path delays occur due to the time required for signals to propagate through each of the plurality of circuit elements from the input to the output of the signal path. Each circuit element has its own switching delay known as the switching delay of a circuit element. This circuit element switching delay is the time required for a circuit element to switch logic states from either a high-to-low logic state (logic 1→0) or from a low-to-high logic state (logic 0→1). The path switching delay is determined by the accumulation of time it takes for a signal to pass through each of the circuit elements in a particular path. This time, in turn, is based on the total switching delay of each circuit element in the path. Paths with the highest number of combined switching delays of circuit elements are known as speed paths or critical paths. These critical paths dictate how fast an integrated circuit can operate. The maximum frequency an integrated circuit can operate at depends directly on how fast signals can propagate across the worst-case critical paths.
FIG. 1A illustrates the switching of static logic states for a series of inverters according to the prior art. Circuit 100 includes a series of connected inverting logic gates 110-1, 110-2, 110-3, 110-4, through 110-n. These inverting logic gates are referred to simply as “inverters” or INV gates. The switching delay experienced by each of these inverters in the path will determine how much time it takes for a signal to propagate from the input IN of inverter 110-1 through to the output (OUT) of inverter 110-n. In the illustrated example, the input to inverter 110-1 switches from a logic state 0 (low) to a logic state 1 (high). This results in the output of inverter 110-1 switching from logic 1 to 0. When the output of logic gate 110-1 transitions from logic 1 to 0, the signal propagates into the input of the next circuit element, inverter 110-2, causing the output of inverter 110-2 to transition from logic 0 to 1. Similarly, logic gate inverter 110-3 causes an inversion on the output that propagates into the input of inverter 110-4 causing an inversion on the output of inverter 110-4, and so on and so forth until the output (OUT) of inverter 110-n is reached. The output of each of the inverters are said to be in an inverting relationship since the output of one inverter causes a corresponding inversion on the output of the next downstream inverter, and so on. Each of these transitions occurs sequentially, one being essentially complete before the other begins. The accumulation of time it takes for each of inverters 110-1 through 110-n to switch (invert) logic states from logic 0 to logic 1, or from logic 1 to logic 0 is the total switching delay of the circuit path shown in FIG. 1A. Hence, FIG. 1A demonstrates the switching of static logic states in the case of a series of inverters, which requires a long switching time before valid data appears at the end of the series of inverters 110-1 through 110-n. The path switching delay is the accumulation of all switching delays of each of the inverters 110-1 through 110-n. This path switching delay occurs not only for inverters, but for any inverting logic functions such as NAND gates, NOR gates, AOI (and-or-invert), OAI (or-and-invert), and etcetera.
Switching delays may be optimized in order to facilitate a signal propagating along a critical path from input to output with reduced switching delays. Conventionally, circuit path delays are optimized in two ways. The first way is to reduce the number of logic stages by combining multiple stages into a single stage. The second way is to reduce the amount of switching delay that a particular stage requires. Such reduction in delay can be accomplished using several techniques known in the art such as transistor resizing, reducing output load, improving input transition time, breaking the complex cells into simpler cells, and etcetera.
Other methods to reduce the switching delays of the logic gates in a path include precharging logic gates (i.e., dynamic logic) and skewing logic gates through transistor resizing. In the case of using dynamic logic, a method for optimizing switching delays of a path in an integrated circuit using dynamic logic gates includes using output prediction logic (OPL) circuits. In OPT circuits every logic gate includes dynamic logic with a precharge circuit. FIG. 1B illustrates a method for optimizing switching delay of logic gates in a circuit path using output prediction logic (OPL) according to the prior art. Circuit 140 includes inverters 150-1, 150-2, 150-3, 150-4, through 150-n. Each inverter includes clock inputs CK 160-1, CK 160-2, CK 160-3, CK 160-4, through CK 160-n respectively that are supplied to precharge circuits in each inverter (not shown) to precharge the output of all the logic gates to a certain value (usually logic=1) during a precharge phase of the clock inputs. In order to facilitate the OPL method, delayed clocks with a small difference in delay are provided to enable each stage in succession so that a reduced number of outputs potentially switch states. It is noted that, because the logic gates are precharged to logic 1, switching of the logic states is avoided on the output of logic gates 150-2 and 150-4. As a result, OPL is faster than the regular static logic gates shown in FIG. 1A.
U.S. Pat. No. 6,549,038 entitled, “Method of High Performance CMOS Design,” discloses optimizing signal path delays using the OPL method. However, in OPL circuits there is a somewhat cumbersome requirement of clock signal generation with a very small delay difference between two consecutive logic stages that results in the need to design each clock path with some precision. The generation of clocks with such small delay difference is not straight forward and requires complicated techniques like Delay Locked Loops (DLLs) and carefully designed clock networks. Secondly, the need to supply every stage with a separate clock signal adds to a substantial clocking overhead in the design that requires extra metal resources and careful routing. Also, there are serious concerns about sensitivity to process variation and noise since any significant glitching variation could trigger a regenerative cascading effect across the path. These issues and possibly others may give rise to adoption challenges among the IC design community for this technique. U.S. Pat. No. 6,980,033 entitled, “Pseudo CMOS Dynamic Logic With Delayed Clocks,” discloses circuitry similar to the OPL, technique, but using pseudo-CMOS logic gates instead of CMOS.